In this disclosure, the term “data storage array” has been used to represent a memory sub-system in a more generic sense. The term “data storage element” has been used to indicate a circuit element that stores a single data bit (such as a single memory cell). “Data read-write element” refers to the minimum collection of data storage elements on which an operation (read or write) can be performed (e.g. a byte or a word). As is well known, any read/write operation on a data read-write element actually involves the accessing of multiple data read-write elements internally (e.g. an entire row or column or byte slice) of which only one data read-write element is finally brought-out or updated. This collection of data read-write elements that are accessed together is termed as a “data access element”.
There has been active development in the field of in-field testing and repair for embedded data storage arrays. The primary method relies on a BIST (Built-in Self Test) mechanism which verifies the internal functioning of the embedded data storage array and identifies the failed data storage elements. The BIST structure verifies the data storage array by applying a series of test patterns sequentially across the entire data storage array or across a large portion of it, and comparing the output obtained against the output expected and flagging an incorrect response as a test failure.
The use of a BIST mechanism enables the data storage array sub-system to self-test thereby reducing dependency on other circuits for testing and also reduces the number of clock cycles/clock-cycle-duration required for testing. This also helps in reducing the complexity of the circuit and decreases the time required for testing considerably.
As integrated circuit feature sizes shrink and memory capacity increases, the likelihood of a defect occurring in a data storage array system greatly increases. In order to maintain desired production yield, redundancy is Built-into the data storage array so that defective data storage elements cells can be replaced. The redundancy usually includes a number of spare data access elements within the data storage array that can be selected to replace corresponding defective units during operation.
While using the BIST circuitry for redundancy and repair, the BIST controller captures and decodes the failing addresses, and logs them in a register during the production test. The data is then loaded into a repair mechanism that automatically configures the memory by substituting the failed memory cells with redundant data access elements of the data storage array.
In some cases, the register which stores the failing data is also called the overflow bit register. The overflow bit indicates a condition where more data access elements have failed than can be replaced by the redundant data access elements, leading to an inability to repair. This bit can be read by a connected tester which monitors the test.
FIG. 1 shows a conventional system for “fixing” defective data storage elements which comprises an embedded volatile data storage array such as SRAM, DRAM etc., a BIST, and allocation logic 101 coupled to a data storage array and test circuitry. The test circuitry tests each output bit line of the data storage array. Each output of the allocation logic is coupled to the first input of a series of 2:1 multiplexers 102 (0), 102 (1), . . . 102(n) and an LSSD (Level Sensitive Scannable Design) or a failing bit register comprising master/slave latches L1, L2 103. The second input of each multiplexer is coupled to the output of a slave latch L2. The output of the last slave latch is fed-back to the second input of the first multiplexer. Once the BIST finishes the test cycle, a counter 104 is enabled which changes the selected input of each multiplexer to create a cyclic serial shift register. The counter then provides the shift pulses. A fail counter 105 located on chip counts the number of times a defective data storage element has been encountered. In case the defect i.e. fail count exceeds the number of redundant data access elements, an overflow flag is set by the fail counter 105 indicating that the defective data access elements in the data storage array cannot be repaired. A connected tester then examines the fail counter and determines whether the data storage array is repairable or not. This category of systems and methods used for test and repair requires the use of an external tester and circuitry to interface to the tester which increases chip area. Also the application of the BIST over the entire data storage array increases the time taken to identify defective elements in the data storage array.
The BIST approach cannot be applied while the data storage array is in use since it involves writing to the entire or a large part of the data storage array. This overwrites the stored data and also takes considerable time for the testing. Therefore in-field testing using the BIST approach is limited to testing the data storage array only at power-up or during initialization. Owing to this limitation the BIST approach is unable to detect defects which arise due to temperature variations and voltage fluctuations while the data storage array is in use.
Therefore, there is a need for a system and method, which improves the efficiency of test and restoration of data storage array embedded on chip.